The present invention relates to a semiconductor device, and particularly relates to a semiconductor device having I.sup.2 L (Integrated Injection Logic) gate.
Since, as well known, the I.sup.2 L gate is a bipolar circuit and a simply structured logic circuit which does not need isolation of transistors, it is possible to reduce power consumption and to increase integration density, and the gate has been widely used for the semiconductor integrated circuits.
A conventional I.sup.2 L gate structure will simply be explained with reference to FIGS. 3 and 4. FIG. 3 is a cross sectional view showing an I.sup.2 L gate device structure and FIG. 4 is an equivalent circuit diagram thereof.
As shown in FIG. 3, on an N.sup.+ type silicon substrate 1, an N type epitaxial layer 2 is deposited, and on the epitaxial layer 2, P type impurity diffusion layers 3 and 4 are formed respectively. Further, two N type impurity diffusion layers 5 are formed in a region of the impurity diffusion layer 4. In the Figure, the hatching region shown by reference numeral Tr1 constitutes a PNP type lateral transistor. Also, the hatching region shown by reference numeral Tr2 constitutes an NPN type transistor whose direction is reversed to that of a usual planar type transistor. As apparent from the Figure, a base region and a collector region of the lateral PNP transistor Tr1 are also used for an emitter region and a base region of the reverse NPN transistor Tr2 respectively, so that the isolation and the wiring of each transistor are omitted.
As shown in FIG. 4, the lateral PNP transistor Tr1 is operated as a constant current source and the direction of the collector current is changed by the voltage applied to terminal B. Namely, when a low level voltage is applied to the terminal B, the collector current of the transistor Tr1 flows to an input terminal B side and the reverse NPN transistor Tr2 becomes an OFF state so that a high level voltage is outputted to collector terminals C.sub.1 and C.sub.2. On the contrary, when a high level voltage is applied to the terminal B, the collector current of the transistor Tr1 flows to the base of the transistor Tr2 and the transistor Tr2 becomes an ON state so that a low level voltage is outputted to the collector terminals C.sub.1 and C.sub.2. Thus, the I.sup.2 L gate is basically an inverter, but gates such as OR, NOR etc. can be constituted by combining it.
However, such structured conventional gate has the following problems.
This kind of logic gate is expected to have as high speed operation as possible. Therefore, a way of reducing base resistance by increasing the impurity concentration in the base region is considered, but since the conventional I.sup.2 L gate is structured by homojunction of silicon crystal, when the impurity concentration in the base region is increased too much, reverse injection of carriers (holes in the NPN transistor and electrons in the PNP transistor) from the base region to the emitter region is increased and the injection efficiency in the emitter is lowered. As a result, the current gain (h.sub.FE) is disadvantageously decreased. Since in the conventional I.sup.2 L gate, the impurity concentration in the base region cannot be too increased, high speed operation could not be easily realized.